1. Field of the Invention
The invention relates generally to clock circuits, and more particularly to a frequency divider for a phase-locked loop (PLL) based clock generator circuit.
2. Description of the Related Art
A phase-locked loop (PLL) is a circuit which causes a particular system to track with another one. More precisely, a PLL is a circuit synchronizing an output signal (generated by an oscillator) with a reference or input signal in frequency as well as in phase. In the synchronized (often called locked) state, the phase error between the oscillator""s output signal and the reference signal is zero, or remains constant.
If a phase error builds up, a control mechanism acts on the oscillator in such a way that the phase error is again reduced to a minimum. In such a control system the phase of the output signal is actually locked to the phase of the reference signal.
Obtaining the maximum performance or speed for the least amount of power is a goal in chip design. Typically, a clock is generated using a phase-locked loop and then distributed to various circuits on a chip. Not all circuits on a chip are driven by clocks at the same frequency. A significant improvement in system performance can be obtained by increasing the clock frequency that is input to certain circuits. Many circuits on a chip may require one clock frequency while other circuits may require a multiple of that clock frequency or a different clock frequency. There are often difficulties associated with generating a wide range of multiples of a clock frequency.